Phase, frequency, and amplitude of grid voltage are important information in grid-connected photovoltaic systems. For proper and stable operation of a system, a fast and correct estimation of grid information under grid variations and disturbances is very crucial. In this paper, an adaptive phase-locked loop (PLL) structure is proposed which tracks the phase jumps of grid voltage fast and smoothly. If a jump occurs in grid voltage phase transient state at the frequency estimation of frequency lock loop (FLL) will be almost zero. The settling times of the estimated phase, frequency, and amplitude of the proposed PLL are also slightly low. The proposed PLL consists of the second-order generalized integrator (SOGI) and frequency locked loop (FLL). The whole system has been simulated in MATLAB/Simulink. The settling time of estimated frequency and amplitude for proposed PLL are 0.023 and 0.024 s, respectively.

To benefit form advantages of parallel operation of diesel-generators, their rapid and smooth synchronization is required. A new method in design and implementation of such a synchronizer, based on phase locked loop (PLL), is described and test results are presented.The synchronizer automatically controls the generator to achieve zero phase difference, and then issues the synchronization command. The main advantage of the method over other synchronizers is to lock on the perfect synchronous state using PLL. Thus, there is no need to consider circuit breaker operating time and to estimate proper synchronization instant. The result is faster and more reliable synchronization as compared to the existing types.

A fast settling multi-standard CMOS fractional-N frequency synthesizer for DECT, GSM, CDMA and NADC wireless communication standards is proposed. This frequency synthesizer was simulated with ADS2008 in TSMC RF CMOS 0. 18 µ m. Frequency range is 824-1900 MHz, a switched capacitor LC-VCO was used in order to produce this frequency range. Frequency synthesizers have three main specifications of phase noise, settling time and power consumption. A new channel select circuit was designed instead of ∑ ∆ modulator to locate spur tones far from center frequency. A high reference frequency was used in order to reduce the VCO phase noise and locate the spur tones far from center frequency; these tones are produced by charge pump (reference spur) and N/N+1 divider (fractional spur). Two ways were used for phase noise optimization; in the first way phase noise was reduced by a low pass filter and a bypass capacitor (CT) that eliminate thermal noise and 2ω 0 harmonics of tail current source; in the second way with biasing of VCO transistors only in saturation region preventing reduction of quality factor(Q) in tank circuit. These two ways in VCO of DECT were used, consequently the phase noise at 1875MHz center frequency was improved from-119. 4 dBc/Hz at 3. 4 MHz offset frequency to-144. 3 dBc/Hz at 3. 4 MHz offset frequency. The settling time for all standards was achieved less than almost 1 μ s over the entire frequency range. For DECT synthesizer phase noise of-116. 37 dBc/Hz at 3 MHz offset frequency was obtained, the first spur tone was located in 7. 35 MHz offset from center frequency, also settling time of 350ns was obtained. The whole frequency synthesizer in loop1 (for DECT) draws 13 mA and in loop2 (for GSM900, CDMA & NADC) draws 13. 67 mA from a 1. 8 V voltage supply.

This paper presents the design and simulation of a phase-locked loop (PLL) with a center frequency of 2.45 GHz, implemented using 0.18 µm CMOS technology and HSPICE simulation tools. The proposed PLL architecture comprises key components including a phase detector, charge pump, low-pass filter, voltage-controlled oscillator, and frequency divider. Circuit parameters were meticulously optimized through extensive simulations to ensure high performance. Results demonstrate stable and precise operation, with a power consumption below 13.56 mW, a lock time of approximately 16 reference cycles, and a phase noise of −115 dBc/Hz at 1 MHz offset. Owing to its low power usage and robust stability, the design is well-suited for applications such as ADSL modems, Wi-Fi communication systems, and portable electronic devices.

This article presents development and implementation of an integer N-type Phase Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a phase noise better than -110dBC/Hz@10k. The structure has 0 and 10dBm power levels at 1 and 4GHz output frequencies, respectively. Having two different outputs of 1 and 4 GHz at once, in addition to the 1.1 and 4.4GHz realized by the capability included in this design in which two additional outputs can be achieved by using the pins A0 to A4 and altering their status, makes this structure a good candidate for mass production. A two-step frequency division is employed in this work. The first step is realized using the frequency divider of order 4, and the second step is implemented inside the HMC440 IC, including a PFD and a counter. Compared to typical methods, this method presents a clean output by suppressing the spurs meant to be manifested using a single-step frequency division. This PLL is constructed in discrete and modular modes and employed in transceivers’ up-converter and down-converter blocks, Satellite communications, Cable TV links (CATV), Local Area Networks (LAN), Global Positioning Systems (GPS), test equipment, digital radios, military and commercial communications. For a specific example, the 4GHz frequency is used to up-converte or down-converte the received signals, and the 1-GHz frequency is usually used for the synthesizer module clock frequency. Advanced Design System (ADS) was used in the design, and OrCAD was used in the schematic design of the PLL module.

Phase locked loops (PLL) are widely used in telecommunication systems. Frequency characteristics and settling time are the two most important features of PLLs. In phase lock loops, several nonlinear factors can be considered, one of which is the nonlinear behavior of the phase detector. In fact, load pump phase locking loops (CPPLL) are nonlinear systems due to the nonlinear behavior generated by the load pump. Although the applied current is fixed in an ideal load pump, this is not fixed in practice because of the non-ideal behavior of the transistors. In this paper, considering the channel length modulation (CLM) effect caused by the drain-source voltage of MOSFET transistor, a more accurate model is presented for the phase detector. By investigating the non-linear differential equation dominating the system and using the step-response approximation for the transient time analysis, new equations are obtained for the settling time and overshooting. In order to check the validity of the specified non-linear equations, the simulation was conducted in MATLAB Simulink. Moreover, in order to better assess the proposed method, the performance of a PLL subjected to the transistor’ s drain-source voltage has been simulated and the effect of the different loop parameters, such as the loop’ s resistor and current has been investigated. The final results showed the appropriate accordance of the analytical equations with the simulation results.

This paper presents the design and simulation of a high-performance fractional-N phase-locked loop (PLL) frequency synthesizer with a 60 kHz bandwidth, operating within a frequency range of 2.4 GHz to 2.5 GHz. The design integrates advanced features such as a sigma-delta modulator configured in a 1-1-1 MASH architecture and a fractional divider, both implemented with intelligent control circuits to precisely determine the division ratio. These innovations aim to reduce delay and power consumption while enhancing phase noise performance and ensuring robust system stability. The fractional divider is a critical component of the PLL, enabling frequency division into fractional values with high precision. By incorporating intelligent control circuits, the design achieves accurate adjustments to the division ratio, contributing significantly to the overall reliability and efficiency of the PLL. Additionally, integrating advanced modulation and filtering techniques further optimizes the loop's performance by suppressing unwanted noise and ensuring stability under varying conditions. Simulation results demonstrate the effectiveness of the proposed design, achieving a fast frequency lock time of approximately 3 µs, a stable phase margin of 45 degrees, and an impressive phase noise performance of -148.13 dBc/Hz at a 1 MHz offset. Furthermore, the system's total power consumption is only 2.36 mW, highlighting its exceptional balance between power efficiency and high performance.

In this paper, a new scheme named "modified coherent DiLL" is proposed for tracking direction of arrival of signals in direct-sequence code-division multiple-access systems. This scheme has a similar concept to the delay lock loop that is used for time synchronizing in CDMA systems. The proposed scheme is able to track the DOA of the arriving signals iteratively. The properties of the proposed scheme such as computational and mean square error are compared to the coherent and noncoherent DiLL. The new scheme consists of 2NK+O(K) computations, where Nand K are the number of antenna sensors and signal sources, respectively. The computation is two-folds and approximately the same Mean Square error as coherent DiLL scheme, while it does not require estimating. Data and phase of the received carrier signal. In addition, the computation of this method is approximately equal, and mean square error is half of the noncoherent DiLL.

Single-phase voltage source inverters (SP-VSIs) are widely used in grid connected solar photovoltaic (PV) systems. This paper deals with the dynamic modeling and stability analysis of single-phase grid connected PV inverters taking the PLL dynamics into account. The PLL structure employed in this paper includes two control branches; the main branch, known as phase estimation loop, extracts the phase and frequency of the grid voltage and the other branch, known as voltage peak estimation loop, determines the grid voltage amplitude. In this way, the paper first proposes design considerations for the dc-link voltage control and PLL control loops. Then, unified dynamic modeling of the SP-VSI system comprising PLL, dc-link dynamics and grid is presented and linearized block diagram of the whole system is extracted. The linearized block diagram depicts the interaction between the control loops of the PLL and dc-link system, where the PLL control loops consist of phase/frequency and amplitude estimation loops of the grid voltage. Next, the small signal stability of the full system is presented, and impacts of grid strength, operating point, and PLL closed loop bandwidth on the performance of SP-VSI are investigated by the modal analysis and time domain simulations.